Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die.
The resolution of the printed circuit is often the limiting factor controlling interconnect density. The above-incorporated patent applications disclose substrates and processes for making substrates having embedded conductors.
However, the embossing process described in the above-incorporated parent applications requires special tooling and has limitations on conductor size that are related to the material used for the dielectric. The laser-ablation processes described in the above-incorporated parent applications requires a very high power laser in order to ablate the dielectric material and has consequent speed limitations that lower throughput. The ablation of the dielectric material also limits the possible conductor density because of the difficulties associated with cleanly ablating the dielectric material.
Therefore, it would be desirable to provide an embedded-conductor substrate manufacturing process having improved conductor density, manufacturing throughput and a low associated manufacturing cost. It would further be desirable to provide such a process that does not require a high power laser.